On Uniformly Sampling Traces of a Transition System (Extended Version)

A key problem in constrained random verification (CRV) concerns generation of input stimuli that result in good coverage of the system's runs in targeted corners of its behavior space. Existing CRV solutions however provide no formal guarantees on the distribution of the system's runs. In this paper, we take a first step towards solving this problem. We present an algorithm based on Algebraic Decision Diagrams for sampling bounded traces (i.e. sequences of states) of a sequential circuit with provable uniformity (or bias) guarantees, while satisfying given constraints. We have implemented our algorithm in a tool called TraceSampler. Extensive experiments show that TraceSampler outperforms alternative approaches that provide similar uniformity guarantees.Comment: Extended version of paper that will appear in proceedings of International Conference on Computer-Aided Design (ICCAD '20); changed wrong text color in sec 7; added 'extended version

Technology Mapping using Fuzzy Logic

Abstract- This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring loads (derived from a dynamically updated placement) and used by the mapper to calculate the signal arrival times. In the process we describe a number of fuzzy operations which are needed to generate the fuzzy delay curves and to select a minimum area mapping solution satisfying a set of timing constraints. This procedure has been implemented and the results are on average 1% and 26 % (5 % and 3%)better in terms of area and delay compared to a technology mapping procedure with zero (crisp) wire load values.

PLA Minimization for Low Power VLSI Designs

In this paper we study the problem of optimizing the two-level representation of a Boolean function in order to minimize power consumption in PLAs. We first give power models used to estimate the power consumption in pseudo-NMOS and dynamic PLAs. Using these power cost functions we then prove that a minimum power solution for dynamic PLAs consists only of prime implicants of the function. For pseudo-NMOS PLAs we show that for incompletely specified multiple output functions, the minimal solution may contain non-prime implicants. We then describe exact and heuristic solutions for minimizing the power consumption of a Boolean function implemented using PLAs. We finally use the results of our experiments to draw conclusions on the effectiveness of low power two-level function minimization for PLAs. 2 3 1 Introduction Recent advances and trends in the electronics industry has made power consumption an important factor in the design of digital systems. Increasing popularity of portabl..

RPM: A rapid prototyping engine for multiprocessor systems

In multiprocessor systems, processing nodes contain a processor, some cache and a share of the system memory, and are connected through a scalable interconnect. The system memory partitions may be shared (shared-memory systems) or disjoint (messagepassing systems). Within each class of systems many architectural variations are possible. Fair comparisons among systems are difficult because of the lack of a common hardware platform to implement the different architectures. RPM (Rapid Prototyping engine for Multiprocessors) is a hardware emulator for the rapid prototyping of various multiprocessor architectures. In RPM, the hardware of the target machine is emulated by reprogrammable controllers implemented with Field-Programmable Gate Arrays (FPGAs). The processors, memories and interconnect are off-theshelf and their relative speeds can be modified to emulate various component technologies. Every emulation is an actual incarnation of the target machine and therefore software written for the target machine can be easily ported on it with little modification and without instrumentation of the code. In this paper, we describe the architecture of RPM, its performance and the prototyping methodology. We also compare our approach with simulation and breadboard prototyping. Keywords: Field-Programmable Gate Arrays (FPGAs), message-passing multicomputers, shared-memory multiprocessors, design verification, performance evaluation, simulation

Polystyrene/Polyolefin Elastomer Blends Loaded with Halloysite Nanotubes: Morphological, Mechanical, and Gas Barrier Properties

Abstract Herein, a simple melt‐blending method is utilized to disperse of halloysite nanotubes (HNTs) in polystyrene/polyolefin elastomer (PS/POE) blends. Based on morphological studies, the PS/POE/HNT nanocomposite containing up to 3 phr HNTs shows excellent nanofiller dispersion, while those filled with 5 phr HNTs exhibit nanofiller aggregation. To overcome the nanofiller aggregation issue, the polypropylene‐grafted‐maleic anhydride (PP‐g‐MA) compatibilizer is added to the PS/POE/HNT nanocomposite, which results in improved mechanical properties for the nanocomposite sheets. Furthermore, the addition of compatibilized HNTs to the PS/POE blends leads to decreased O2 and N2 gas permeabilities. Besides, incorporating POE, HNTs, and PP‐g‐MA leads to a decrease in water vapor transmission of PS. In the end, the experimentally‐determined mechanical properties and gas permeabilities of the nanocomposite sheets are compared to those predicted by prevalent theoretical models, revealing a good agreement between the experimental and theoretical results. Molecular‐dynamics simulations are also carried out to calculate the gas diffusion coefficients in the different sheets to further support the experimental findings in this study. Overall, the PS/POE/HNT/PP‐g‐MA nanocomposite sheets fabricated in this work demonstrate excellent mechanical and gas barrier properties; and hence, can be used as candidate packaging materials. However, the strength of the resulting PS/POE blend may be inferior to that of the virgin PS

Combinational Circuit Optimization

Introduction Low power VLSI design can be achieved at various levels of the design abstraction from algorithmic and system levels down to layout and circuit levels (see Figure 1). Power optimization techniques at the system, architectural (behavioral) design level, register-transfer (RT) level, physical design level, and the circuit level have been addressed by researchers in the past. Logic synthesis however, is an important part of the design cycle for a digital system. This means that in order to minimize power effectively, power has to be considered during logic synthesis and optimization. Logic synthesis provides the automatic synthesis of gate-level netlists, minimizing some objective function subject to various constraints. The goal, in general is to obtain a minimum area circuit subject to a given delay requirement. Example inputs to a logic synthesis system include two-level logic representation, multi-level Boolean networks, finite state machines and technology mapped circ